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41
7674F–AVR–09/09
ATmega164P/324P/644P
8.
Power Management and Sleep Modes
8.1
Overview
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving-
power. The AVR provides various sleep modes allowing the user to tailor the power
consumption to the application’s requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during
the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
See “BOD Disable” on page 42 for more details.
8.2
Sleep Modes
Figure 7-1 on page 29 presents the different clock systems in the ATmega164P/324P/644P, and
their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 8-1 shows
the different sleep modes, their wake up sources and BOD disable ability.
Notes:
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt.
To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP
instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which
sleep mode will be activated by the SLEEP instruction. See Table 8-2 on page 46 for a
summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Table 8-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
So
ft
wa
re
BOD
Disda
b
le
Sleep Mode
clk
CPU
clk
FLASH
clk
IO
clk
AD
C
clk
ASY
Main
Clo
c
k
So
ur
c
e
En
a
b
le
d
Time
rOsc
En
a
b
le
d
INT2:
0
and
Pi
n
C
h
a
n
g
e
TWI
Ad
d
re
ss
Matc
h
Time
r2
SP
M
/
E
EPR
O
M
R
ead
y
ADC
WD
T
Int
e
rrupt
Ot
her
I/O
Idle
X
X(2)
XXXXXXX
ADCNRM
X
X(2)
X(3)
XX(2)
XXX
Power-down
X(3)
XX
X
Power-save
X
X(2)
X(3)
XX
X
Standby(1)
XX(3)
XX
X
Extended
Standby
X(2)
XX(2)
X(3)
XX
X
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